e1000_ich8lan.c 175 KB
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/******************************************************************************
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  SPDX-License-Identifier: BSD-3-Clause
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  Copyright (c) 2001-2020, Intel Corporation
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  All rights reserved.
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  Redistribution and use in source and binary forms, with or without
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  modification, are permitted provided that the following conditions are met:
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   1. Redistributions of source code must retain the above copyright notice,
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      this list of conditions and the following disclaimer.
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   2. Redistributions in binary form must reproduce the above copyright
      notice, this list of conditions and the following disclaimer in the
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      documentation and/or other materials provided with the distribution.
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   3. Neither the name of the Intel Corporation nor the names of its
      contributors may be used to endorse or promote products derived from
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      this software without specific prior written permission.
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  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  POSSIBILITY OF SUCH DAMAGE.

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******************************************************************************/
/*$FreeBSD$*/
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/* 82562G 10/100 Network Connection
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 * 82562G-2 10/100 Network Connection
 * 82562GT 10/100 Network Connection
 * 82562GT-2 10/100 Network Connection
 * 82562V 10/100 Network Connection
 * 82562V-2 10/100 Network Connection
 * 82566DC-2 Gigabit Network Connection
 * 82566DC Gigabit Network Connection
 * 82566DM-2 Gigabit Network Connection
 * 82566DM Gigabit Network Connection
 * 82566MC Gigabit Network Connection
 * 82566MM Gigabit Network Connection
 * 82567LM Gigabit Network Connection
 * 82567LF Gigabit Network Connection
 * 82567V Gigabit Network Connection
 * 82567LM-2 Gigabit Network Connection
 * 82567LF-2 Gigabit Network Connection
 * 82567V-2 Gigabit Network Connection
 * 82567LF-3 Gigabit Network Connection
 * 82567LM-3 Gigabit Network Connection
 * 82567LM-4 Gigabit Network Connection
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 * 82577LM Gigabit Network Connection
 * 82577LC Gigabit Network Connection
 * 82578DM Gigabit Network Connection
 * 82578DC Gigabit Network Connection
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 * 82579LM Gigabit Network Connection
 * 82579V Gigabit Network Connection
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 * Ethernet Connection I217-LM
 * Ethernet Connection I217-V
 * Ethernet Connection I218-V
 * Ethernet Connection I218-LM
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 * Ethernet Connection (2) I218-LM
 * Ethernet Connection (2) I218-V
 * Ethernet Connection (3) I218-LM
 * Ethernet Connection (3) I218-V
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 */

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#include "e1000_api.h"
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static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
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static s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
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static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
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static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
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static int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
static int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
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static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
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static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
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					      u8 *mc_addr_list,
					      u32 mc_addr_count);
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static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
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static s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
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static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
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					    bool active);
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static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
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					    bool active);
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static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
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				   u16 words, u16 *data);
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static s32  e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
			       u16 *data);
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static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
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				    u16 words, u16 *data);
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static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
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static s32  e1000_update_nvm_checksum_spt(struct e1000_hw *hw);
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static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
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					    u16 *data);
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static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
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static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
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static s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
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static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
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					   u16 *speed, u16 *duplex);
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static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
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static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
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static s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
static s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
static s32  e1000_led_on_pchlan(struct e1000_hw *hw);
static s32  e1000_led_off_pchlan(struct e1000_hw *hw);
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static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
static s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
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static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
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static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
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					  u32 offset, u8 *data);
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static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
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					  u8 size, u16 *data);
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static s32  e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
					    u32 *data);
static s32  e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
					   u32 offset, u32 *data);
static s32  e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
					     u32 offset, u32 data);
static s32  e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
						  u32 offset, u32 dword);
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static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
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					  u32 offset, u16 *data);
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static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
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						 u32 offset, u8 byte);
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static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
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static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
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static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
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static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
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static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
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/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
/* Offset 04h HSFSTS */
union ich8_hws_flash_status {
	struct ich8_hsfsts {
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		u16 flcdone:1; /* bit 0 Flash Cycle Done */
		u16 flcerr:1; /* bit 1 Flash Cycle Error */
		u16 dael:1; /* bit 2 Direct Access error Log */
		u16 berasesz:2; /* bit 4:3 Sector Erase Size */
		u16 flcinprog:1; /* bit 5 flash cycle in Progress */
		u16 reserved1:2; /* bit 13:6 Reserved */
		u16 reserved2:6; /* bit 13:6 Reserved */
		u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
		u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
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	} hsf_status;
	u16 regval;
};

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
/* Offset 06h FLCTL */
union ich8_hws_flash_ctrl {
	struct ich8_hsflctl {
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		u16 flcgo:1;   /* 0 Flash Cycle Go */
		u16 flcycle:2;   /* 2:1 Flash Cycle */
		u16 reserved:5;   /* 7:3 Reserved  */
		u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
		u16 flockdn:6;   /* 15:10 Reserved */
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	} hsf_ctrl;
	u16 regval;
};

/* ICH Flash Region Access Permissions */
union ich8_hws_flash_regacc {
	struct ich8_flracc {
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		u32 grra:8; /* 0:7 GbE region Read Access */
		u32 grwa:8; /* 8:15 GbE region Write Access */
		u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
		u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
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	} hsf_flregacc;
	u16 regval;
};

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/**
 *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 *  @hw: pointer to the HW structure
 *
 *  Test access to the PHY registers by reading the PHY ID registers.  If
 *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 *  otherwise assume the read PHY ID is correct if it is valid.
 *
 *  Assumes the sw/fw/hw semaphore is already acquired.
 **/
static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
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{
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	u16 phy_reg = 0;
	u32 phy_id = 0;
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	s32 ret_val = 0;
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	u16 retry_count;
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	u32 mac_reg = 0;
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	for (retry_count = 0; retry_count < 2; retry_count++) {
		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
		if (ret_val || (phy_reg == 0xFFFF))
			continue;
		phy_id = (u32)(phy_reg << 16);
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		ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
		if (ret_val || (phy_reg == 0xFFFF)) {
			phy_id = 0;
			continue;
		}
		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
		break;
	}

	if (hw->phy.id) {
		if  (hw->phy.id == phy_id)
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			goto out;
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	} else if (phy_id) {
		hw->phy.id = phy_id;
		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
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		goto out;
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	}

	/* In case the PHY needs to be in mdio slow mode,
	 * set slow mode and try to get the PHY id again.
	 */
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	if (hw->mac.type < e1000_pch_lpt) {
		hw->phy.ops.release(hw);
		ret_val = e1000_set_mdio_slow_mode_hv(hw);
		if (!ret_val)
			ret_val = e1000_get_phy_id(hw);
		hw->phy.ops.acquire(hw);
	}

	if (ret_val)
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		return false;
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out:
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	if (hw->mac.type >= e1000_pch_lpt) {
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		/* Only unforce SMBus if ME is not active */
		if (!(E1000_READ_REG(hw, E1000_FWSM) &
		    E1000_ICH_FWSM_FW_VALID)) {
			/* Unforce SMBus mode in PHY */
			hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
			phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
			hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
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			/* Unforce SMBus mode in MAC */
			mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
			E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
		}
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	}

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	return true;
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}

/**
 *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 *  @hw: pointer to the HW structure
 *
 *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 *  used to reset the PHY to a quiescent state when necessary.
 **/
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static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
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{
	u32 mac_reg;

	DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");

	/* Set Phy Config Counter to 50msec */
	mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
	mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
	mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
	E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);

	/* Toggle LANPHYPC Value bit */
	mac_reg = E1000_READ_REG(hw, E1000_CTRL);
	mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
	mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
	E1000_WRITE_FLUSH(hw);
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	msec_delay(1);
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	mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
	E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
	E1000_WRITE_FLUSH(hw);

	if (hw->mac.type < e1000_pch_lpt) {
		msec_delay(50);
	} else {
		u16 count = 20;

		do {
			msec_delay(5);
		} while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
			   E1000_CTRL_EXT_LPCD) && count--);
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		msec_delay(30);
	}
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}

/**
 *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 *  @hw: pointer to the HW structure
 *
 *  Workarounds/flow necessary for PHY initialization during driver load
 *  and resume paths.
 **/
static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
{
	u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
	s32 ret_val;

	DEBUGFUNC("e1000_init_phy_workarounds_pchlan");

	/* Gate automatic PHY configuration by hardware on managed and
	 * non-managed 82579 and newer adapters.
	 */
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	e1000_gate_hw_phy_config_ich8lan(hw, true);
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	/* It is not possible to be certain of the current state of ULP
	 * so forcibly disable it.
	 */
	hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
	e1000_disable_ulp_lpt_lp(hw, TRUE);

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	ret_val = hw->phy.ops.acquire(hw);
	if (ret_val) {
		DEBUGOUT("Failed to initialize PHY flow\n");
		goto out;
	}

	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
	 * inaccessible and resetting the PHY is not blocked, toggle the
	 * LANPHYPC Value bit to force the interconnect to PCIe mode.
	 */
	switch (hw->mac.type) {
	case e1000_pch_lpt:
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	case e1000_pch_spt:
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	case e1000_pch_cnp:
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	case e1000_pch_tgp:
	case e1000_pch_adp:
	case e1000_pch_mtp:
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		if (e1000_phy_is_accessible_pchlan(hw))
			break;

		/* Before toggling LANPHYPC, see if PHY is accessible by
		 * forcing MAC to SMBus mode first.
		 */
		mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
		E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);

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		/* Wait 50 milliseconds for MAC to finish any retries
		 * that it might be trying to perform from previous
		 * attempts to acknowledge any phy read requests.
		 */
		 msec_delay(50);

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		/* FALLTHROUGH */
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	case e1000_pch2lan:
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		if (e1000_phy_is_accessible_pchlan(hw))
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			break;

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		/* FALLTHROUGH */
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	case e1000_pchlan:
		if ((hw->mac.type == e1000_pchlan) &&
		    (fwsm & E1000_ICH_FWSM_FW_VALID))
			break;

		if (hw->phy.ops.check_reset_block(hw)) {
			DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
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			ret_val = -E1000_ERR_PHY;
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			break;
		}

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		/* Toggle LANPHYPC Value bit */
		e1000_toggle_lanphypc_pch_lpt(hw);
		if (hw->mac.type >= e1000_pch_lpt) {
			if (e1000_phy_is_accessible_pchlan(hw))
				break;
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			/* Toggling LANPHYPC brings the PHY out of SMBus mode
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			 * so ensure that the MAC is also out of SMBus mode
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			 */
			mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
			E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);

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			if (e1000_phy_is_accessible_pchlan(hw))
				break;

			ret_val = -E1000_ERR_PHY;
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		}
		break;
	default:
		break;
	}

	hw->phy.ops.release(hw);
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	if (!ret_val) {
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		/* Check to see if able to reset PHY.  Print error if not */
		if (hw->phy.ops.check_reset_block(hw)) {
			ERROR_REPORT("Reset blocked by ME\n");
			goto out;
		}

		/* Reset the PHY before any access to it.  Doing so, ensures
		 * that the PHY is in a known good state before we read/write
		 * PHY registers.  The generic reset is sufficient here,
		 * because we haven't determined the PHY type yet.
		 */
		ret_val = e1000_phy_hw_reset_generic(hw);
		if (ret_val)
			goto out;

		/* On a successful reset, possibly need to wait for the PHY
		 * to quiesce to an accessible state before returning control
		 * to the calling function.  If the PHY does not quiesce, then
		 * return E1000E_BLK_PHY_RESET, as this is the condition that
		 *  the PHY is in.
		 */
		ret_val = hw->phy.ops.check_reset_block(hw);
		if (ret_val)
			ERROR_REPORT("ME blocked access to PHY after reset\n");
	}
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out:
	/* Ungate automatic PHY configuration on non-managed 82579 */
	if ((hw->mac.type == e1000_pch2lan) &&
	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
		msec_delay(10);
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		e1000_gate_hw_phy_config_ich8lan(hw, false);
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	}

	return ret_val;
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}

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/**
 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific PHY parameters and function pointers.
 **/
static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
{
	struct e1000_phy_info *phy = &hw->phy;
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	s32 ret_val;
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	DEBUGFUNC("e1000_init_phy_params_pchlan");

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	phy->addr		= 1;
	phy->reset_delay_us	= 100;

	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
	phy->ops.set_page	= e1000_set_page_igp;
	phy->ops.read_reg	= e1000_read_phy_reg_hv;
	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
	phy->ops.read_reg_page	= e1000_read_phy_reg_page_hv;
	phy->ops.release	= e1000_release_swflag_ich8lan;
	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
	phy->ops.write_reg	= e1000_write_phy_reg_hv;
	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
	phy->ops.write_reg_page	= e1000_write_phy_reg_page_hv;
	phy->ops.power_up	= e1000_power_up_phy_copper;
	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
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	phy->id = e1000_phy_unknown;
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	ret_val = e1000_init_phy_workarounds_pchlan(hw);
	if (ret_val)
		return ret_val;
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	if (phy->id == e1000_phy_unknown)
		switch (hw->mac.type) {
		default:
			ret_val = e1000_get_phy_id(hw);
			if (ret_val)
				return ret_val;
			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
				break;
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			/* FALLTHROUGH */
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		case e1000_pch2lan:
		case e1000_pch_lpt:
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		case e1000_pch_spt:
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		case e1000_pch_cnp:
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		case e1000_pch_tgp:
		case e1000_pch_adp:
		case e1000_pch_mtp:
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			/* In case the PHY needs to be in mdio slow mode,
			 * set slow mode and try to get the PHY id again.
			 */
			ret_val = e1000_set_mdio_slow_mode_hv(hw);
			if (ret_val)
				return ret_val;
			ret_val = e1000_get_phy_id(hw);
			if (ret_val)
				return ret_val;
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			break;
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		}
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	phy->type = e1000_get_phy_type_from_id(phy->id);

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	switch (phy->type) {
	case e1000_phy_82577:
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	case e1000_phy_82579:
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	case e1000_phy_i217:
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		phy->ops.check_polarity = e1000_check_polarity_82577;
		phy->ops.force_speed_duplex =
			e1000_phy_force_speed_duplex_82577;
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		phy->ops.get_cable_length = e1000_get_cable_length_82577;
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		phy->ops.get_info = e1000_get_phy_info_82577;
		phy->ops.commit = e1000_phy_sw_reset_generic;
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		break;
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	case e1000_phy_82578:
		phy->ops.check_polarity = e1000_check_polarity_m88;
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
		phy->ops.get_cable_length = e1000_get_cable_length_m88;
		phy->ops.get_info = e1000_get_phy_info_m88;
		break;
	default:
		ret_val = -E1000_ERR_PHY;
		break;
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	}

	return ret_val;
}

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/**
 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
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 *  @hw: pointer to the HW structure
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 *
 *  Initialize family-specific PHY parameters and function pointers.
 **/
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static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
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{
	struct e1000_phy_info *phy = &hw->phy;
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	s32 ret_val;
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	u16 i = 0;
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	DEBUGFUNC("e1000_init_phy_params_ich8lan");

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	phy->addr		= 1;
	phy->reset_delay_us	= 100;

	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
	phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
	phy->ops.read_reg	= e1000_read_phy_reg_igp;
	phy->ops.release	= e1000_release_swflag_ich8lan;
	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
	phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
	phy->ops.write_reg	= e1000_write_phy_reg_igp;
	phy->ops.power_up	= e1000_power_up_phy_copper;
	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
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	/* We may need to do this twice - once for IGP and if that fails,
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	 * we'll set BM func pointers and try again
	 */
	ret_val = e1000_determine_phy_address(hw);
	if (ret_val) {
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		phy->ops.write_reg = e1000_write_phy_reg_bm;
		phy->ops.read_reg  = e1000_read_phy_reg_bm;
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		ret_val = e1000_determine_phy_address(hw);
		if (ret_val) {
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			DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
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			return ret_val;
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		}
	}
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	phy->id = 0;
	while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
	       (i++ < 100)) {
		msec_delay(1);
		ret_val = e1000_get_phy_id(hw);
		if (ret_val)
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			return ret_val;
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	}
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	/* Verify phy id */
	switch (phy->id) {
	case IGP03E1000_E_PHY_ID:
		phy->type = e1000_phy_igp_3;
		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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		phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
		phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
		phy->ops.get_info = e1000_get_phy_info_igp;
		phy->ops.check_polarity = e1000_check_polarity_igp;
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
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		break;
	case IFE_E_PHY_ID:
	case IFE_PLUS_E_PHY_ID:
	case IFE_C_E_PHY_ID:
		phy->type = e1000_phy_ife;
		phy->autoneg_mask = E1000_ALL_NOT_GIG;
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		phy->ops.get_info = e1000_get_phy_info_ife;
		phy->ops.check_polarity = e1000_check_polarity_ife;
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
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		break;
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	case BME1000_E_PHY_ID:
		phy->type = e1000_phy_bm;
		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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		phy->ops.read_reg = e1000_read_phy_reg_bm;
		phy->ops.write_reg = e1000_write_phy_reg_bm;
		phy->ops.commit = e1000_phy_sw_reset_generic;
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		phy->ops.get_info = e1000_get_phy_info_m88;
		phy->ops.check_polarity = e1000_check_polarity_m88;
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
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		break;
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	default:
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		return -E1000_ERR_PHY;
		break;
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	}

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	return E1000_SUCCESS;
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}

/**
 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
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 *  @hw: pointer to the HW structure
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 *
 *  Initialize family-specific NVM parameters and function
 *  pointers.
 **/
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static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
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{
	struct e1000_nvm_info *nvm = &hw->nvm;
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	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
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	u32 gfpreg, sector_base_addr, sector_end_addr;
	u16 i;
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	u32 nvm_size;
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	DEBUGFUNC("e1000_init_nvm_params_ich8lan");

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	nvm->type = e1000_nvm_flash_sw;
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	if (hw->mac.type >= e1000_pch_spt) {
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		/* in SPT, gfpreg doesn't exist. NVM size is taken from the
		 * STRAP register. This is because in SPT the GbE Flash region
		 * is no longer accessed through the flash registers. Instead,
		 * the mechanism has changed, and the Flash region access
		 * registers are now implemented in GbE memory space.
		 */
		nvm->flash_base_addr = 0;
		nvm_size =
		    (((E1000_READ_REG(hw, E1000_STRAP) >> 1) & 0x1F) + 1)
		    * NVM_SIZE_MULTIPLIER;
		nvm->flash_bank_size = nvm_size / 2;
		/* Adjust to word count */
		nvm->flash_bank_size /= sizeof(u16);
		/* Set the base address for flash register access */
		hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
	} else {
		/* Can't read flash registers if register set isn't mapped. */
		if (!hw->flash_address) {
			DEBUGOUT("ERROR: Flash registers not mapped\n");
			return -E1000_ERR_CONFIG;
		}
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		gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
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		/* sector_X_addr is a "sector"-aligned address (4096 bytes)
		 * Add 1 to sector_end_addr since this sector is included in
		 * the overall size.
		 */
		sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
		sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
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		/* flash_base_addr is byte-aligned */
		nvm->flash_base_addr = sector_base_addr
				       << FLASH_SECTOR_ADDR_SHIFT;

		/* find total size of the NVM, then cut in half since the total
		 * size represents two separate NVM banks.
		 */
		nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
					<< FLASH_SECTOR_ADDR_SHIFT);
		nvm->flash_bank_size /= 2;
		/* Adjust to word count */
		nvm->flash_bank_size /= sizeof(u16);
	}
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	nvm->word_size = E1000_SHADOW_RAM_WORDS;
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	/* Clear shadow ram */
	for (i = 0; i < nvm->word_size; i++) {
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		dev_spec->shadow_ram[i].modified = false;
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		dev_spec->shadow_ram[i].value    = 0xFFFF;
	}

	/* Function Pointers */
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	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;
	nvm->ops.release	= e1000_release_nvm_ich8lan;
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	if (hw->mac.type >= e1000_pch_spt) {
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		nvm->ops.read	= e1000_read_nvm_spt;
		nvm->ops.update	= e1000_update_nvm_checksum_spt;
	} else {
		nvm->ops.read	= e1000_read_nvm_ich8lan;
		nvm->ops.update	= e1000_update_nvm_checksum_ich8lan;
	}
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	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
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	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;
	nvm->ops.write		= e1000_write_nvm_ich8lan;
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	return E1000_SUCCESS;
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}

/**
 *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
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 *  @hw: pointer to the HW structure
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 *
 *  Initialize family-specific MAC parameters and function
 *  pointers.
 **/
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static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
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{
	struct e1000_mac_info *mac = &hw->mac;

	DEBUGFUNC("e1000_init_mac_params_ich8lan");

	/* Set media type function pointer */
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	hw->phy.media_type = e1000_media_type_copper;
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	/* Set mta register count */
	mac->mta_reg_count = 32;
	/* Set rar entry count */
	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
	if (mac->type == e1000_ich8lan)
		mac->rar_entry_count--;
	/* Set if part includes ASF firmware */
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	mac->asf_firmware_present = true;
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	/* FWSM register */
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	mac->has_fwsm = true;
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	/* ARC subsystem not supported */
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	mac->arc_subsystem_valid = false;
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	/* Adaptive IFS supported */
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	mac->adaptive_ifs = true;
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	/* Function pointers */

	/* bus type/speed/width */
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	mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
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	/* function id */
	mac->ops.set_lan_id = e1000_set_lan_id_single_port;
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	/* reset */
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	mac->ops.reset_hw = e1000_reset_hw_ich8lan;
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	/* hw initialization */
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	mac->ops.init_hw = e1000_init_hw_ich8lan;
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	/* link setup */
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	mac->ops.setup_link = e1000_setup_link_ich8lan;
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	/* physical interface setup */
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	mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
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	/* check for link */
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	mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
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	/* link info */
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	mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
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	/* multicast address update */
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	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
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	/* clear hardware counters */
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	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
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	/* LED and other operations */
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	switch (mac->type) {
	case e1000_ich8lan:
	case e1000_ich9lan:
	case e1000_ich10lan:
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		/* check management mode */
		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
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		/* ID LED init */
		mac->ops.id_led_init = e1000_id_led_init_generic;
		/* blink LED */
		mac->ops.blink_led = e1000_blink_led_generic;
		/* setup LED */
		mac->ops.setup_led = e1000_setup_led_generic;
		/* cleanup LED */
		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
		/* turn on/off LED */
		mac->ops.led_on = e1000_led_on_ich8lan;
		mac->ops.led_off = e1000_led_off_ich8lan;
		break;
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	case e1000_pch2lan:
		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
		mac->ops.rar_set = e1000_rar_set_pch2lan;
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		/* FALLTHROUGH */
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	case e1000_pch_lpt:
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	case e1000_pch_spt:
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	case e1000_pch_cnp:
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	case e1000_pch_tgp:
	case e1000_pch_adp:
	case e1000_pch_mtp:
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		/* multicast address update for pch2 */
		mac->ops.update_mc_addr_list =
			e1000_update_mc_addr_list_pch2lan;
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		/* FALLTHROUGH */
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	case e1000_pchlan:
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		/* check management mode */
		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
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		/* ID LED init */
		mac->ops.id_led_init = e1000_id_led_init_pchlan;
		/* setup LED */
		mac->ops.setup_led = e1000_setup_led_pchlan;
		/* cleanup LED */
		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
		/* turn on/off LED */
		mac->ops.led_on = e1000_led_on_pchlan;
		mac->ops.led_off = e1000_led_off_pchlan;
		break;
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	default:
		break;
	}

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	if (mac->type >= e1000_pch_lpt) {
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		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
		mac->ops.rar_set = e1000_rar_set_pch_lpt;
		mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
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		mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
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	}

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	/* Enable PCS Lock-loss workaround for ICH8 */
	if (mac->type == e1000_ich8lan)
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		e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
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	return E1000_SUCCESS;
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}

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/**
 *  __e1000_access_emi_reg_locked - Read/write EMI register
 *  @hw: pointer to the HW structure
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 *  @address: EMI address to program
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 *  @data: pointer to value to read/write from/to the EMI address
 *  @read: boolean flag to indicate read or write
 *
 *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 **/
static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
					 u16 *data, bool read)
{
	s32 ret_val;

	DEBUGFUNC("__e1000_access_emi_reg_locked");

	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
	if (ret_val)
		return ret_val;

	if (read)
		ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
						      data);
	else
		ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
						       *data);

	return ret_val;
}

/**
 *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 *  @hw: pointer to the HW structure
 *  @addr: EMI address to program
 *  @data: value to be read from the EMI address
 *
 *  Assumes the SW/FW/HW Semaphore is already acquired.
 **/
s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
{
	DEBUGFUNC("e1000_read_emi_reg_locked");

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	return __e1000_access_emi_reg_locked(hw, addr, data, true);
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}

/**
 *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 *  @hw: pointer to the HW structure
 *  @addr: EMI address to program
 *  @data: value to be written to the EMI address
 *
 *  Assumes the SW/FW/HW Semaphore is already acquired.
 **/
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s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
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{
	DEBUGFUNC("e1000_read_emi_reg_locked");

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	return __e1000_access_emi_reg_locked(hw, addr, &data, false);
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}

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/**
 *  e1000_set_eee_pchlan - Enable/disable EEE support
 *  @hw: pointer to the HW structure
 *
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 *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 *  the link and the EEE capabilities of the link partner.  The LPI Control
 *  register bits will remain set only if/when link is up.
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 *
 *  EEE LPI must not be asserted earlier than one second after link is up.
 *  On 82579, EEE LPI should not be enabled until such time otherwise there
 *  can be link issues with some switches.  Other devices can have EEE LPI
 *  enabled immediately upon link up since they have a timer in hardware which
 *  prevents LPI from being asserted too early.
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 **/
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s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
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{
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	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
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	s32 ret_val;
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	u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
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	DEBUGFUNC("e1000_set_eee_pchlan");

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	switch (hw->phy.type) {
	case e1000_phy_82579:
		lpa = I82579_EEE_LP_ABILITY;
		pcs_status = I82579_EEE_PCS_STATUS;
		adv_addr = I82579_EEE_ADVERTISEMENT;
		break;
	case e1000_phy_i217:
		lpa = I217_EEE_LP_ABILITY;
		pcs_status = I217_EEE_PCS_STATUS;
		adv_addr = I217_EEE_ADVERTISEMENT;
		break;
	default:
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		return E1000_SUCCESS;
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	}
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	ret_val = hw->phy.ops.acquire(hw);
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	if (ret_val)
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		return ret_val;
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	ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
	if (ret_val)
		goto release;

	/* Clear bits that enable EEE in various speeds */
	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;

	/* Enable EEE if not disabled by user */
	if (!dev_spec->eee_disable) {
		/* Save off link partner's EEE ability */
		ret_val = e1000_read_emi_reg_locked(hw, lpa,
						    &dev_spec->eee_lp_ability);
		if (ret_val)
			goto release;

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		/* Read EEE advertisement */
		ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
		if (ret_val)
			goto release;

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		/* Enable EEE only for speeds in which the link partner is
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		 * EEE capable and for which we advertise EEE.
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		 */
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		if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
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			lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;

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		if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
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			hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
			if (data & NWAY_LPAR_100TX_FD_CAPS)
				lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
			else
				/* EEE is not supported in 100Half, so ignore
				 * partner's EEE in 100 ability if full-duplex
				 * is not advertised.
				 */
				dev_spec->eee_lp_ability &=
				    ~I82579_EEE_100_SUPPORTED;
		}
	}

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	if (hw->phy.type == e1000_phy_82579) {
		ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
						    &data);
		if (ret_val)
			goto release;

		data &= ~I82579_LPI_100_PLL_SHUT;
		ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
						     data);
	}

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	/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
	ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
	if (ret_val)
		goto release;

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	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
release:
	hw->phy.ops.release(hw);
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