Commit 6030b0c6 authored by Mark Johnston's avatar Mark Johnston
Browse files

Flush caches before initiating a microcode update on Intel CPUs.

This apparently works around issues with updates of certain Broadwell

Reviewed by:	emaste, kib, sbruno
MFC after:	3 days
Differential Revision:
parent db5a36bd
......@@ -367,8 +367,10 @@ update_intel(int cpu, cpuctl_update_args_t *args, struct thread *td)
rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current microcode revision. */
* Perform update.
* Perform update. Flush caches first to work around seeingly
* undocumented errata applying to some Broadwell CPUs.
wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr));
wrmsr_safe(MSR_BIOS_SIGN, 0);
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