Commit 65618fdd authored by Michal Meloun's avatar Michal Meloun
Browse files

arm64: Initialize VFP control register.

The RW fields in this register reset to architecturally unknown values,
so initialize these to the proper rounding and denormal mode.
MFC after:	1 week
parent c1b13547
...@@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$"); ...@@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$");
#include <sys/proc.h> #include <sys/proc.h>
#include <machine/armreg.h> #include <machine/armreg.h>
#include <machine/md_var.h>
#include <machine/pcb.h> #include <machine/pcb.h>
#include <machine/vfp.h> #include <machine/vfp.h>
...@@ -238,6 +239,9 @@ vfp_init(void) ...@@ -238,6 +239,9 @@ vfp_init(void)
/* Disable to be enabled when it's used */ /* Disable to be enabled when it's used */
vfp_disable(); vfp_disable();
if (PCPU_GET(cpuid) == 0)
thread0.td_pcb->pcb_fpusaved->vfp_fpcr = initial_fpcr;
} }
SYSINIT(vfp, SI_SUB_CPU, SI_ORDER_ANY, vfp_init, NULL); SYSINIT(vfp, SI_SUB_CPU, SI_ORDER_ANY, vfp_init, NULL);
......
...@@ -55,6 +55,8 @@ __FBSDID("$FreeBSD$"); ...@@ -55,6 +55,8 @@ __FBSDID("$FreeBSD$");
#include <machine/vfp.h> #include <machine/vfp.h>
#endif #endif
uint32_t initial_fpcr = VFPCR_DN | VFPCR_FZ;
#include <dev/psci/psci.h> #include <dev/psci/psci.h>
/* /*
...@@ -106,6 +108,7 @@ cpu_fork(struct thread *td1, struct proc *p2, struct thread *td2, int flags) ...@@ -106,6 +108,7 @@ cpu_fork(struct thread *td1, struct proc *p2, struct thread *td2, int flags)
td2->td_pcb->pcb_sp = (uintptr_t)td2->td_frame; td2->td_pcb->pcb_sp = (uintptr_t)td2->td_frame;
td2->td_pcb->pcb_fpusaved = &td2->td_pcb->pcb_fpustate; td2->td_pcb->pcb_fpusaved = &td2->td_pcb->pcb_fpustate;
td2->td_pcb->pcb_vfpcpu = UINT_MAX; td2->td_pcb->pcb_vfpcpu = UINT_MAX;
td2->td_pcb->pcb_fpusaved->vfp_fpcr = initial_fpcr;
/* Setup to release spin count in fork_exit(). */ /* Setup to release spin count in fork_exit(). */
td2->td_md.md_spinlock_count = 1; td2->td_md.md_spinlock_count = 1;
......
...@@ -54,4 +54,6 @@ void generic_bs_poke_2(void) __asm(__STRING(generic_bs_poke_2)); ...@@ -54,4 +54,6 @@ void generic_bs_poke_2(void) __asm(__STRING(generic_bs_poke_2));
void generic_bs_poke_4(void) __asm(__STRING(generic_bs_poke_4)); void generic_bs_poke_4(void) __asm(__STRING(generic_bs_poke_4));
void generic_bs_poke_8(void) __asm(__STRING(generic_bs_poke_8)); void generic_bs_poke_8(void) __asm(__STRING(generic_bs_poke_8));
extern uint32_t initial_fpcr;
#endif /* !_MACHINE_MD_VAR_H_ */ #endif /* !_MACHINE_MD_VAR_H_ */
...@@ -32,6 +32,29 @@ ...@@ -32,6 +32,29 @@
#ifndef _MACHINE_VFP_H_ #ifndef _MACHINE_VFP_H_
#define _MACHINE_VFP_H_ #define _MACHINE_VFP_H_
/* VFPCR */
#define VFPCR_AHP (0x04000000) /* alt. half-precision: */
#define VFPCR_DN (0x02000000) /* default NaN enable */
#define VFPCR_FZ (0x01000000) /* flush to zero enabled */
#define VFPCR_RMODE_OFF 22 /* rounding mode offset */
#define VFPCR_RMODE_MASK (0x00c00000) /* rounding mode mask */
#define VFPCR_RMODE_RN (0x00000000) /* round nearest */
#define VFPCR_RMODE_RPI (0x00400000) /* round to plus infinity */
#define VFPCR_RMODE_RNI (0x00800000) /* round to neg infinity */
#define VFPCR_RMODE_RM (0x00c00000) /* round to zero */
#define VFPCR_STRIDE_OFF 20 /* vector stride -1 */
#define VFPCR_STRIDE_MASK (0x00300000)
#define VFPCR_LEN_OFF 16 /* vector length -1 */
#define VFPCR_LEN_MASK (0x00070000)
#define VFPCR_IDE (0x00008000) /* input subnormal exc enable */
#define VFPCR_IXE (0x00001000) /* inexact exception enable */
#define VFPCR_UFE (0x00000800) /* underflow exception enable */
#define VFPCR_OFE (0x00000400) /* overflow exception enable */
#define VFPCR_DZE (0x00000200) /* div by zero exception en */
#define VFPCR_IOE (0x00000100) /* invalid op exec enable */
#ifndef LOCORE #ifndef LOCORE
struct vfpstate { struct vfpstate {
__uint128_t vfp_regs[32]; __uint128_t vfp_regs[32];
......
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