Commit d5ad2f2a authored by Wenzhuo Lu's avatar Wenzhuo Lu Committed by Kevin Bowling
Browse files

e1000: fix K1 configuration



This patch is for the following updates to the K1 configurations:
Tx idle period for entering K1 should be 128 ns.
Minimum Tx idle period in K1 should be 256 ns.

Signed-off-by: default avatarWenzhuo Lu <wenzhuo.lu@intel.com>

PR:		258153
Reviewed by:	erj
Tested by:	iron.udjin@gmail.com
Approved by:	imp
Obtained from:	DPDK (6f934fa24dfd437c90ead96bc7598ee77a117ede)
MFC after:	1 week
parent f555b39e
......@@ -1728,7 +1728,6 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
if (ret_val)
return ret_val;
}
/* Clear link partner's EEE ability */
hw->dev_spec.ich8lan.eee_lp_ability = 0;
......@@ -1749,6 +1748,9 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
/* Configure K0s minimum time */
e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
}
if (!link)
......@@ -6144,3 +6146,44 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
}
}
/**
* e1000_configure_k0s_lpt - Configure K0s power state
* @hw: pointer to the HW structure
* @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
* 0 corresponds to 128ns, each value over 0 doubles the duration.
* @min_time: Minimum Tx idle period allowed - valid values are 0 to 4.
* 0 corresponds to 128ns, each value over 0 doubles the duration.
*
* Configure the K1 power state based on the provided parameter.
* Assumes semaphore already acquired.
*
* Success returns 0, Failure returns:
* -E1000_ERR_PHY (-2) in case of access error
* -E1000_ERR_PARAM (-4) in case of parameters error
**/
s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
{
s32 ret_val;
u16 kmrn_reg = 0;
DEBUGFUNC("e1000_configure_k0s_lpt");
if (entry_latency > 3 || min_time > 4)
return -E1000_ERR_PARAM;
ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
&kmrn_reg);
if (ret_val)
return ret_val;
/* for now don't touch the latency */
kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
kmrn_reg);
if (ret_val)
return ret_val;
return E1000_SUCCESS;
}
......@@ -337,6 +337,7 @@ void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time);
void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
......
......@@ -281,6 +281,13 @@ s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */
#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
#define E1000_KMRNCTRLSTA_K0S_CTRL 0x1E /* Kumeran K0s Control */
#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT 0
#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT 4
#define E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_MASK \
(3 << E1000_KMRNCTRLSTA_K0S_CTRL_ENTRY_LTNCY_SHIFT)
#define E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK \
(7 << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT)
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
......
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