1. 10 Aug, 2017 2 commits
    • royger's avatar
      x86: bump MAX_APIC_ID to 512 · 55936e52
      royger authored
      Introduce a new define to take int account the xAPIC ID limit, for
      systems where x2APIC is not available/reliable.
      Also change some of the usages of the APIC ID to use an unsigned int
      (which is the correct storage type to deal with x2APIC IDs as found in
      x2APIC MADT entries).
      This allows booting FreeBSD on a box with 256 CPUs and APIC IDs up to
      FreeBSD/SMP: Multiprocessor System Detected: 256 CPUs
      FreeBSD/SMP: 1 package(s) x 64 core(s) x 4 hardware threads
      Package HW ID = 0
      	Core HW ID = 0
      		CPU0 (BSP): APIC ID: 0
      		CPU1 (AP/HT): APIC ID: 1
      		CPU2 (AP/HT): APIC ID: 2
      		CPU3 (AP/HT): APIC ID: 3
      	Core HW ID = 73
      		CPU252 (AP): APIC ID: 292
      		CPU253 (AP/HT): APIC ID: 293
      		CPU254 (AP/HT): APIC ID: 294
      		CPU255 (AP/HT): APIC ID: 295
      Submitted by:		kib (previous version)
      Relnotes:		yes
      MFC after:		1 month
      Reviewed by:		kib
      Differential revision:	https://reviews.freebsd.org/D11913
    • royger's avatar
      apic_enumerator: only set mp_ncpus and mp_maxid at probe cpus phase · 345fb326
      royger authored
      Populate the lapics arrays and call cpu_add/lapic_create in the setup
      phase instead. Also store the max APIC ID found in the newly
      introduced max_apic_id global variable.
      This is a requirement in order to make the static arrays currently
      using MAX_LAPIC_ID dynamic.
      Sponsored by:		Citrix Systems R&D
      MFC after:		1 month
      Reviewed by:		kib
      Differential revision:	https://reviews.freebsd.org/D11911
  2. 28 Jan, 2017 1 commit
  3. 15 Jan, 2017 1 commit
  4. 27 May, 2016 1 commit
  5. 21 Feb, 2014 1 commit
  6. 27 Dec, 2013 1 commit
  7. 11 Dec, 2013 1 commit
  8. 09 Dec, 2013 1 commit
  9. 16 Jul, 2011 1 commit
  10. 15 Jul, 2011 1 commit
    • jhb's avatar
      Respect the BIOS/firmware's notion of acceptable address ranges for PCI · b75d5a0e
      jhb authored
      resource allocation on x86 platforms:
      - Add a new helper API that Host-PCI bridge drivers can use to restrict
        resource allocation requests to a set of address ranges for different
        resource types.
      - For the ACPI Host-PCI bridge driver, use Producer address range resources
        in _CRS to enumerate valid address ranges for a given Host-PCI bridge.
        This can be disabled by including "hostres" in the debug.acpi.disabled
      - For the MPTable Host-PCI bridge driver, use entries in the extended
        MPTable to determine the valid address ranges for a given Host-PCI
        bridge.  This required adding code to parse extended table entries.
      Similar to the new PCI-PCI bridge driver, these changes are only enabled
      if the NEW_PCIB kernel option is enabled (which is enabled by default on
      amd64 and i386).
      Approved by:	re (kib)
  11. 09 Nov, 2010 1 commit
  12. 08 Nov, 2010 1 commit
    • jhb's avatar
      Sync the APIC startup sequence with amd64: · bfc0fcbf
      jhb authored
      - Register APIC enumerators at SI_SUB_TUNABLES - 1 instead of SI_SUB_CPU - 1.
      - Probe CPUs at SI_SUB_TUNABLES - 1.  This allows i386 to set a truly
        accurate mp_maxid value rather than always setting it to MAXCPU - 1.
  13. 01 Nov, 2010 1 commit
  14. 28 Oct, 2010 1 commit
  15. 19 Oct, 2010 1 commit
  16. 19 Mar, 2010 1 commit
  17. 22 Nov, 2008 1 commit
  18. 19 Oct, 2008 1 commit
  19. 22 Jul, 2008 1 commit
    • rwatson's avatar
      Merge r177253, r177255 from head to stable/7: · 97ddbbd5
      rwatson authored
        In keeping with style(9)'s recommendations on macros, use a ';'
        after each SYSINIT() macro invocation.  This makes a number of
        lightweight C parsers much happier with the FreeBSD kernel
        source, including cflow's prcc and lxr.
        Discussed with: imp, rink
      The requirement to place a ; after each SYSINIT definition has not been
      MFC'd, as this might break the compile third-party modules, but merging
      the actual ; additions reduces diffs against 8.x making it easier to
      merge other changes.
  20. 16 Mar, 2008 1 commit
  21. 05 Oct, 2007 1 commit
  22. 08 May, 2007 1 commit
    • jhb's avatar
      Handle CPUs with APIC IDs higher than 32 (at least one IBM server uses · 255387b6
      jhb authored
      an APIC ID of 38 for its second CPU):
      - Add a new MAX_APIC_ID constant for the highest valid APIC ID for modern
      - Size the various arrays in the MADT, MP Table, and SMP code that are
        indexed by APIC IDs to allow for up to MAX_APIC_ID.
      - Explicitly go through and assign logical cpu ids to local APICs before
        starting any of the APs up rather than doing it while starting up the
        APs.  This step is now where we honor MAXCPU.
      MFC after:	1 week
  23. 09 Mar, 2007 1 commit
  24. 05 Mar, 2007 1 commit
  25. 31 Oct, 2005 1 commit
    • rwatson's avatar
      Normalize a significant number of kernel malloc type names: · be4f3571
      rwatson authored
      - Prefer '_' to ' ', as it results in more easily parsed results in
        memory monitoring tools such as vmstat.
      - Remove punctuation that is incompatible with using memory type names
        as file names, such as '/' characters.
      - Disambiguate some collisions by adding subsystem prefixes to some
        memory types.
      - Generally prefer lower case to upper case.
      - If the same type is defined in multiple architecture directories,
        attempt to use the same name in additional cases.
      Not all instances were caught in this change, so more work is required to
      finish this conversion.  Similar changes are required for UMA zone names.
  26. 14 Apr, 2005 1 commit
  27. 10 Feb, 2005 1 commit
  28. 18 Jan, 2005 1 commit
    • jhb's avatar
      If a valid ELCR was found, consult it for the trigger mode of ISA · eb5749cd
      jhb authored
      interrupts that have a trigger mode of conforming.  This fixes problems on
      some older machines that still route PCI devices via ISA interrupts when
      using an I/O APIC.
      Tested by:	Peter Trifonov pvtrifonov at mail dot ru
      MFC after:	1 month
  29. 12 Jan, 2005 1 commit
    • jhb's avatar
      Try harder to work with MP table interrupt entries that claim that an · 2411c5a7
      jhb authored
      interrupt is wired up to all the I/O APICs in the system.  If the system
      has only one I/O APIC, then just act as if the entry specified that APIC.
      We still don't try to handle global entries in a system with multiple I/O
      Tested by:	Peter Trifonov pvtrifonov at mail dot ru
      MFC after:	1 week
  30. 07 Jan, 2005 1 commit
    • jhb's avatar
      Fix support for machines with default MP Table configurations: · 0e5c952f
      jhb authored
      - Fix the MP Table pci bridge drivers to not probe the configuration table
        unless we actually have one.  Machines using a default configuration do
        not have such a table.
      - Only allow default configuration types of 5 (ISA + PCI) and 6 (EISA +
        PCI) as the others are not likely to work.  Types 1 through 4 use an
        external APIC (probably with 80486 processors) which we certainly do not
        support, and type 7 uses an MCA bus which has not been tested with the
        new MP Table code.
      - Correct the fact that the single I/O APIC in a default configuration has
        an ID of 2, not 0.
      - Fix off by one errors in setting the bus types from the default_data[]
        arrays for default configurations.
      - Explicitly configure each of the 16 interrupt pins on the sole I/O APIC
        when using a default configuration.  This is especially helpful for type
        6 (EISA + PCI) since the EISA interrupts need to have their polarity
        programmed based on the values in the ELCR.
      Much thanks to the submitter and tester who endured several rounds of
      testing to get this fixed.
      MFC after:	1 week
      Tested by:	Georg Schwarz georg dot schwarz at freenet dot de
  31. 24 Sep, 2004 1 commit
  32. 01 Jul, 2004 1 commit
  33. 23 Jun, 2004 1 commit
    • jhb's avatar
      Various cleanups in support of a future ioapic_config_intr() function: · 22d8e1a7
      jhb authored
      - Allow ioapic_set_{nmi,smi,extint}() to be called multiple times on the
        same pin so long as the pin's mode is the same as the mode being
      - Add a notion of bus type for the interrupt associated with interrupt pin.
        This is needed so that we can force all EISA interrupts to be active high
        in the forthcoming ioapic_config_intr().
      - Fix a bug for EISA systems that didn't remap IRQs.  This would have broken
        EISA systems that tried to disable mixed mode for IRQ 0.
  34. 24 May, 2004 1 commit
    • jhb's avatar
      Revert part of rev 1.230 and assume that all EISA IRQs use active high · c6ce1616
      jhb authored
      polarity rather than assuming that level triggered IRQs use active low and
      edge triggered IRQs use active high.  Both the MultiProcessor 1.4
      and ACPI 2.0 Specifications state in their examples that level triggered
      EISA IRQs are active low, but in practice they seem to be active high.
      Reported by:	Nik Azim Azam nskyline_r35 at yahoo dot com
  35. 10 May, 2004 1 commit
    • jhb's avatar
      Rework the APIC mixed mode support a bit: · 3564a344
      jhb authored
      - Require the APIC enumerators to explicitly enable mixed mode by calling
        ioapic_enable_mixed_mode().  Calling this function tells the apic driver
        that the PC-AT 8259A PICs are present and routable through the first I/O
        APIC via an ExtINT pin.  The mptable enumerator always calls this
        function for now.  The MADT enumerator only enables mixed mode if the
        PC-AT compatability flag is set in the MADT header.
      - Allow mixed mode to be enabled or disabled via a 'hw.apic.mixed_mode'
        tunable.  By default this tunable is set to 1 (true).  The kernel option
        NO_MIXED_MODE changes the default to 0 to preserve existing behavior, but
        adding 'hw.apic.mixed_mode=0' to loader.conf achieves the same effect.
      - Only use mixed mode to route IRQ 0 if it is both enabled by the APIC
        enumerator and activated by the loader tunable.  Note that both
        conditions must be true, so if the APIC enumerator does not enable mixed
        mode, then you can't set the tunable to try to override the enumerator.
  36. 06 May, 2004 1 commit
  37. 04 May, 2004 1 commit
    • jhb's avatar
      - Change the APIC code to mostly use the recently added intr_trigger · e0774953
      jhb authored
        and intr_polarity enums for passing around interrupt trigger modes and
        polarity rather than using the magic numbers 0 for level/low and 1 for
      - Convert the mptable parsing code to use the new ELCR wrapper code rather
        than reading the ELCR directly.  Also, use the ELCR settings to control
        both the trigger and polarity of EISA IRQs instead of just the trigger
      - Rework the MADT's handling of the ACPI SCI again:
        - If no override entry for the SCI exists at all, use level/low trigger
          instead of the default edge/high used for ISA IRQs.
        - For the ACPI SCI, use level/low values for conforming trigger and
          polarity rather than the edge/high values we use for all other ISA
        - Rework the tunables available to override the MADT.  The
          hw.acpi.force_sci_lo tunable is no longer supported.  Instead, there
          are now two tunables that can independently override the trigger mode
          and/or polarity of the SCI.  The hw.acpi.sci.trigger tunable can be
          set to either "edge" or "level", and the hw.acpi.sci.polarity tunable
          can be set to either "high" or "low".  To simulate hw.acpi.force_sci_lo,
          set hw.acpi.sci.trigger to "level" and hw.acpi.sci.polarity to "low".
          If you are having problems with ACPI either causing an interrupt storm
          or not working at all (e.g., the power button doesn't turn invoke a
          shutdown -p now), you can try tweaking these two tunables to find the
          combination that works.
  38. 10 Dec, 2003 1 commit
  39. 03 Dec, 2003 1 commit
    • jhb's avatar
      - Reorder the APIC enumerator SYSINIT's to register enumeators at · bfe6af52
      jhb authored
        SI_SUB_CPU - 1 and probe enumerators, probe CPUs, and setup the local
        APIC programming all at SI_SUB_CPU / SI_ORDER_FIRST.  This is needed to
        help get the ACPI module working again as it moves the APIC enumeration
        code after SI_SUB_KLD.
      - In the MADT parser, use mp_maxid rather than MAXCPU to terminate a loop
        when assigning per-cpu ACPI IDs to avoid a dependency on 'options SMP'.
      - Allow the apic device to be disabled via 'hint.apic.0.disabled' from the
        loader.  Note that since this is done in the local APIC code, it works
        for both the ACPI and non-ACPI cases.
      Approved by:	re (scott / blanket)