ns8250 code. We will need to think of a better way for
code reuse for this (see sys/mips/rmi/uart_cpu_mips_xlr.c for where
it is used)

Submitted by:	bde@

the includes point to the new place.

has nothing to do with the rollover.

Approved by: imp (mentor)

the board specific environment variables.

This is not ar71xx specific and should be shared better.

booting, before dynamic kenv is running. A few platforms implement their own
scratch+sprintf handling to save data from the boot environment.

Remove needless braces.

  addresses and could modify areas of memory that share the same cache
  line at the beginning and at the ending of the buffer. In order to
  prevent a data loss we save these chunks in temporary buffer before
  invalidation and restore them afer it.

Idea suggested by: cognet

- Add mips_picache_linesize and mips_pdcache_linesize variables

- minor style(9) fix

calls us to fix it, we then issue a read for a full sector and then copy in/out
the payload. This will happen if Redboot is compiled with
CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG.

- Some minor style(9) fixes

The "_MTC0 v0, COP_0_TLB_HI" is actually incorrect because v0 has not been
initialized at that point. It worked correctly because we subsequently
did the right thing and initialized TLB_HI correctly.

The "li v0, MIPS_KSEG0_START" is redundant because we do exactly the same
thing 2 instructions down.

Approved by: imp (mentor)

SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE

Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.

Approved by: imp (mentor)

    mergeinfo is already in place

kernel.

The SWARM kernel does not build yet but at least it gets past the kernel
config stage.

Approved by: imp (mentor)

    in cpu_switch and use it in stack_trace function later. pcb_regs contains
    state of the process stored by exception handler and therefor is not
    valid for sleeping processes.

present even though the line size field in the CP0 Config1 register is 0.

Approved by: imp (mentor)

"First free SDRAM address" reported by YAMON is 0x800b6e61.

So use a conservative KERNLOADADDR of 0x80100000.

Approved by: imp (mentor)

pcb regs.

64-bit mips.

work for 64-bit compiles.

    Context info could be obtained from other sources (see below) no only from
    td_pcb field
- Do not show a0..a3 values unless they're obtained from the stack. These
    are only confirmed values.
- Fix bt command in DDB. Previous implementation used thread's trapframe
    structure as a source info for trace unwinding, but this structure
    is filled only when exception occurs. Valid register values for sleeping
    processes are in pcb_context array. For curthread use pc/sp/ra for current
    frame

compile and many of them may disappear. For example
the xlr_boot1_console.c is old code that is ifdef'd out.
I will clean these sorts of things up as I make progress
on the port. So far the only thing I have I think straightened
out is the bits around the interupt handling... and hey that
may be broke ;-)

This has a security device and the gig ethernet device.
Note the 10gig device driver is yet missing.

that will need working on to fit from 6.x -> head. But first
I must get the base to compile (wanted to get as much in the tree
as I could before my flight to India).