1. 30 Oct, 2009 4 commits
  2. 29 Oct, 2009 7 commits
  3. 28 Oct, 2009 8 commits
  4. 27 Oct, 2009 1 commit
  5. 26 Oct, 2009 2 commits
  6. 25 Oct, 2009 2 commits
  7. 22 Oct, 2009 2 commits
    • Neel Natu's avatar
      Remove redundant instructions from tlb.S · abd74e0c
      Neel Natu authored
      The "_MTC0 v0, COP_0_TLB_HI" is actually incorrect because v0 has not been
      initialized at that point. It worked correctly because we subsequently
      did the right thing and initialized TLB_HI correctly.
      
      The "li v0, MIPS_KSEG0_START" is redundant because we do exactly the same
      thing 2 instructions down.
      
      Approved by: imp (mentor)
      abd74e0c
    • Neel Natu's avatar
      Get rid of the hardcoded constants to define cacheable memory: · 24c8d4c1
      Neel Natu authored
      SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE
      
      Instead we now keep a copy of the memory regions enumerated by
      platform-specific code and use that to determine whether an address
      is cacheable or not.
      
      Approved by: imp (mentor)
      24c8d4c1
  8. 21 Oct, 2009 2 commits
  9. 20 Oct, 2009 3 commits
  10. 18 Oct, 2009 4 commits
  11. 17 Oct, 2009 1 commit
    • Oleksandr Tymoshenko's avatar
      - Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe. · 4e6df327
      Oleksandr Tymoshenko authored
          Context info could be obtained from other sources (see below) no only from
          td_pcb field
      - Do not show a0..a3 values unless they're obtained from the stack. These
          are only confirmed values.
      - Fix bt command in DDB. Previous implementation used thread's trapframe
          structure as a source info for trace unwinding, but this structure
          is filled only when exception occurs. Valid register values for sleeping
          processes are in pcb_context array. For curthread use pc/sp/ra for current
          frame
      4e6df327
  12. 16 Oct, 2009 1 commit
  13. 15 Oct, 2009 3 commits