- Register APIC enumerators at SI_SUB_TUNABLES - 1 instead of SI_SUB_CPU - 1.
- Probe CPUs at SI_SUB_TUNABLES - 1.  This allows i386 to set a truly
  accurate mp_maxid value rather than always setting it to MAXCPU - 1.

Sponsored by:	Sandvine Incorporated
Discussed with:	jhb

performance in Xen's HVM mode.

  In keeping with style(9)'s recommendations on macros, use a ';'
  after each SYSINIT() macro invocation.  This makes a number of
  lightweight C parsers much happier with the FreeBSD kernel
  source, including cflow's prcc and lxr.

  Discussed with: imp, rink

The requirement to place a ; after each SYSINIT definition has not been
MFC'd, as this might break the compile third-party modules, but merging
the actual ; additions reduces diffs against 8.x making it easier to
merge other changes.

after each SYSINIT() macro invocation.  This makes a number of
lightweight C parsers much happier with the FreeBSD kernel
source, including cflow's prcc and lxr.

MFC after:	1 month
Discussed with:	imp, rink

an APIC ID of 38 for its second CPU):
- Add a new MAX_APIC_ID constant for the highest valid APIC ID for modern
  systems.
- Size the various arrays in the MADT, MP Table, and SMP code that are
  indexed by APIC IDs to allow for up to MAX_APIC_ID.
- Explicitly go through and assign logical cpu ids to local APICs before
  starting any of the APs up rather than doing it while starting up the
  APs.  This step is now where we honor MAXCPU.

MFC after:	1 week

printf.  Otherwise, printfs inside of lapic_init() (such as during a
verbose boot) can uglify the output.

APICs to lapic_init() and ioapic_create().

- Prefer '_' to ' ', as it results in more easily parsed results in
  memory monitoring tools such as vmstat.

- Remove punctuation that is incompatible with using memory type names
  as file names, such as '/' characters.

- Disambiguate some collisions by adding subsystem prefixes to some
  memory types.

- Generally prefer lower case to upper case.

- If the same type is defined in multiple architecture directories,
  attempt to use the same name in additional cases.

Not all instances were caught in this change, so more work is required to
finish this conversion.  Similar changes are required for UMA zone names.

when using an APIC.  This simplifies the APIC code somewhat and also allows
us to be pedantically more compliant with ACPI which mandates no use of
mixed mode.

Found by:	src/tools/tools/kernxref

interrupts that have a trigger mode of conforming.  This fixes problems on
some older machines that still route PCI devices via ISA interrupts when
using an I/O APIC.

Tested by:	Peter Trifonov pvtrifonov at mail dot ru
MFC after:	1 month

interrupt is wired up to all the I/O APICs in the system.  If the system
has only one I/O APIC, then just act as if the entry specified that APIC.
We still don't try to handle global entries in a system with multiple I/O
APICs.

Tested by:	Peter Trifonov pvtrifonov at mail dot ru
MFC after:	1 week

- Fix the MP Table pci bridge drivers to not probe the configuration table
  unless we actually have one.  Machines using a default configuration do
  not have such a table.
- Only allow default configuration types of 5 (ISA + PCI) and 6 (EISA +
  PCI) as the others are not likely to work.  Types 1 through 4 use an
  external APIC (probably with 80486 processors) which we certainly do not
  support, and type 7 uses an MCA bus which has not been tested with the
  new MP Table code.
- Correct the fact that the single I/O APIC in a default configuration has
  an ID of 2, not 0.
- Fix off by one errors in setting the bus types from the default_data[]
  arrays for default configurations.
- Explicitly configure each of the 16 interrupt pins on the sole I/O APIC
  when using a default configuration.  This is especially helpful for type
  6 (EISA + PCI) since the EISA interrupts need to have their polarity
  programmed based on the values in the ELCR.

Much thanks to the submitter and tester who endured several rounds of
testing to get this fixed.

MFC after:	1 week
Tested by:	Georg Schwarz georg dot schwarz at freenet dot de

for the same PCI interrupt.

Tested by:	Pavel Gubin pg at ie dot tusur dot ru
MFC after:	3 days

cut down on the clutter including PCI interrupt routing, MTRR, pcibios,
etc.

Discussed with:	USENIX Cabal

- Allow ioapic_set_{nmi,smi,extint}() to be called multiple times on the
  same pin so long as the pin's mode is the same as the mode being
  requested.
- Add a notion of bus type for the interrupt associated with interrupt pin.
  This is needed so that we can force all EISA interrupts to be active high
  in the forthcoming ioapic_config_intr().
- Fix a bug for EISA systems that didn't remap IRQs.  This would have broken
  EISA systems that tried to disable mixed mode for IRQ 0.

polarity rather than assuming that level triggered IRQs use active low and
edge triggered IRQs use active high.  Both the MultiProcessor 1.4
and ACPI 2.0 Specifications state in their examples that level triggered
EISA IRQs are active low, but in practice they seem to be active high.

Reported by:	Nik Azim Azam nskyline_r35 at yahoo dot com

- Require the APIC enumerators to explicitly enable mixed mode by calling
  ioapic_enable_mixed_mode().  Calling this function tells the apic driver
  that the PC-AT 8259A PICs are present and routable through the first I/O
  APIC via an ExtINT pin.  The mptable enumerator always calls this
  function for now.  The MADT enumerator only enables mixed mode if the
  PC-AT compatability flag is set in the MADT header.
- Allow mixed mode to be enabled or disabled via a 'hw.apic.mixed_mode'
  tunable.  By default this tunable is set to 1 (true).  The kernel option
  NO_MIXED_MODE changes the default to 0 to preserve existing behavior, but
  adding 'hw.apic.mixed_mode=0' to loader.conf achieves the same effect.
- Only use mixed mode to route IRQ 0 if it is both enabled by the APIC
  enumerator and activated by the loader tunable.  Note that both
  conditions must be true, so if the APIC enumerator does not enable mixed
  mode, then you can't set the tunable to try to override the enumerator.

  and intr_polarity enums for passing around interrupt trigger modes and
  polarity rather than using the magic numbers 0 for level/low and 1 for
  edge/high.
- Convert the mptable parsing code to use the new ELCR wrapper code rather
  than reading the ELCR directly.  Also, use the ELCR settings to control
  both the trigger and polarity of EISA IRQs instead of just the trigger
  mode.
- Rework the MADT's handling of the ACPI SCI again:
  - If no override entry for the SCI exists at all, use level/low trigger
    instead of the default edge/high used for ISA IRQs.
  - For the ACPI SCI, use level/low values for conforming trigger and
    polarity rather than the edge/high values we use for all other ISA
    IRQs.
  - Rework the tunables available to override the MADT.  The
    hw.acpi.force_sci_lo tunable is no longer supported.  Instead, there
    are now two tunables that can independently override the trigger mode
    and/or polarity of the SCI.  The hw.acpi.sci.trigger tunable can be
    set to either "edge" or "level", and the hw.acpi.sci.polarity tunable
    can be set to either "high" or "low".  To simulate hw.acpi.force_sci_lo,
    set hw.acpi.sci.trigger to "level" and hw.acpi.sci.polarity to "low".
    If you are having problems with ACPI either causing an interrupt storm
    or not working at all (e.g., the power button doesn't turn invoke a
    shutdown -p now), you can try tweaking these two tunables to find the
    combination that works.

doing the HTT fixup.   This is a step closer to possibly having an apic.ko
module someday.

  SI_SUB_CPU - 1 and probe enumerators, probe CPUs, and setup the local
  APIC programming all at SI_SUB_CPU / SI_ORDER_FIRST.  This is needed to
  help get the ACPI module working again as it moves the APIC enumeration
  code after SI_SUB_KLD.
- In the MADT parser, use mp_maxid rather than MAXCPU to terminate a loop
  when assigning per-cpu ACPI IDs to avoid a dependency on 'options SMP'.
- Allow the apic device to be disabled via 'hint.apic.0.disabled' from the
  loader.  Note that since this is done in the local APIC code, it works
  for both the ACPI and non-ACPI cases.

Approved by:	re (scott / blanket)

field of %.*s rather than size_t.

mistake I did and then committing it to cvs.

if the bus number doesn't correspond to a PCI bus in the MP Table.

Reported by:	jhay

should only be used if they are enabled in the BIOS.  Now that we support
enumerating CPUs using the ACPI MADT, any HTT machine using ACPI should
respect the BIOS setting.  For HTT machines with ACPI disabled in the
kernel, the MPTABLE_FORCE_HTT kernel option can be used to try to probe HTT
CPUs like have done in the past for the MP Table case.  This option should
only be enabled if HTT is enabled in the BIOS.

IDs for the I/O APICs that are greater than 16.

Reported by:	John Cagle <john.cagle@hp.com>

pin that is used by the default identity mapping if it still maps to the
old vector.  The ACPI case might need some tweaking for the SCI interrupt
case since ACPI likes to address the intpin using both the IRQ remapped to
it as well as the previous existing PCI IRQ mapped to it.

Reported by:	kan

the same APIC / pin destination in both cases.

Reported by:	Pawel Jakub Dawidek <nick@garage.freebsd.pl>

enumerate I/O APICs as well as local APICs.  It also provides Host-PCI
and PCI-PCI bridge drivers to use the MP Table to route PCI interrupts.

machine/segments.h.

avoid problems with some Pentium 4 cpus and some older PPro/Pentium2
cpus.  There are several problems, some documented in Intel errata.
This patch:
1) moves the kernel to the second page in the PSE case.  There is an
errata that says that you Must Not point a 4MB page at physical
address zero on older cpus.  We avoided bugs here due to sheer luck.
2) sets up PSE page tables right from the start in locore, rather than
trying to switch from 4K to 4M (or 2M) pages part way through the boot
sequence at the same time that we're messing with PG_G.

For some reason, the pmap work over the last 18 months seems to tickle
the problems, and the PAE infrastructure changes disturb the cpu
bugs even more.

A couple of people have reported a problem with APM bios calls during
boot.  I'll work with people to get this resolved.

Obtained from:	bmilekic

was added.

Requested by:	bde