console, it calls the grab functions. These functions should turn off
the RX interrupts, and any others that interfere. This makes mountroot
prompt work again. If there's more generalized need other than
prompting, many of these routines should be expanded to do those new
things.

Should have been part of r260889, but waasn't due to command line typo.

Reviewed by:	bde (with reservations)

When using DW UART with BUSY detection it is necessary to wait
until all serial transfers are finished before manipulating the
line control. LCR will not be affected when UART is busy.
In addition, if Divisor Latch Access Bit is being set in order to
modify UART divisors:
1. We will get BUSY interrupt if interrupts are enabled.
2. Because LCR will not be affected the THR and (even worse) IER
   contents will be corrupted. This will lead to console hang.

Approved by:	cognet (mentor)

is not giving us a 100% success rate. Bump the delay to 200ms as
that seems to do the trick.

Note that during testing the delay was added to uart_bus_attach()
in uart_core.c. While having the delay in a different place can
change the behaviour, it was not expected. Having to bump the
delay with another 50ms could therefore be an indication that
the problem can not be solved with delays.

Reported by: kevlo@
Tested by: kevlo@

calls ns8250_bus_ipend() almost immediately after ns8250_bus_attach().
As it appears, a line break condition is being signalled for almost
all received characters due to this. A delay of 150ms seems enough
to allow the H/W to settle and to avoid the problem.
More analysis is needed, but for now a regression has been addressed.

Reported by: kevlo@
Tested by: kevlo@

This makes it easier to implement new drivers which are "mostly ns8250"
but with some small difference such as needing to enable clocks or poke
a non-standard register at probe or attach time.

A10 uart is derived from Synopsys DesignWare uart and requires
to read Uart Status Register when IIR_BUSY has detected.
Also this change includes FDT check, where it checks device
specific properties defined in dts and sets the busy_detect variable.
broken_txfifo is also needed to be set in order to make it work for
A10 uart case.

Reviewed by: marcel@
Approved by: gonzo@

bug in old versions of QEMU (and Xen, and other places using QEMU code).
On those buggy emulated UARTs, the "TX idle" interrupt gets lost; with
this workaround, we spinwait for the TX to happen and then send ourselves
the interrupt.  It's ugly but it works, while minimizing the impact on
the code for the !broken_txfifo case.

MFC after:	2 weeks

the IIR_TXRDY bit upon reading.

Reviewed by:	marcel

MCR register on the Sunix Sun1699 chip tends to be set but doesn't
seem to have a function. That is, FreeBSD just works (provided the
correct RCLK is used) regardless.

PR:		kern/129663
Diagnostics:	Eygene Ryabinkin <rea-fbsd at codelabs.ru>
MFC after:	3 days

PR:	bin/154928
Submitted by:	Eitan Adler <lists at eitanadler.com>
MFC after: 	3 days

by /etc/rc.d/jail.

Remove redundant checking of sc_leaving (uart_intr() already handles this).

Approved by:	marcel

ns8250 code. We will need to think of a better way for
code reuse for this (see sys/mips/rmi/uart_cpu_mips_xlr.c for where
it is used)

(framing, parity, etc), but does not indicate characters
being received. Since no chracters have been received,
ignore the line errors.

PR:		131006
MFC after:	3 days

variations from normal 16x50 behaviour however is the the use of a normally
unused bit of IER to control RX timeout interrupts independently of the
generally used RXRDY bit.  If this bit is not enabled, we only ever get
interrupts when the FIFO is full, never before.  This is not very useful when
the UART is being used as a console.

In order to support this without causing potential problems on more "normal"
16x50 variants, this change introduces two hints for the uart device, ier_mask
and ier_rxbits.  These can be used to override which bits get set and cleared
when we're enabling and disabling RX interrupts.

Reviewed by:	marcel

PR:		kern/121421
Submitted by:	UEMURA Tetsuya
Reviewed by:	marcel
MFC after:	2 weeks

in the putc() method.  Likewise, in the getc() method, don't check for
received characters with an interval defined in terms of the baudrate.
In both cases it works equally well to implement a fixed delay.  More
importantly, it avoids calculating a delay that's roughly 1/10th the
time it takes to send/receive a character. The calculation is costly
and happens for every character sent or received, affecting low-level
console or debug port performance significantly. Secondly, when the
RCLK is not available or unreliable, the delays could disrupt normal
operation.

The fixed delay is 1/10th the time it takes to send a character at
230400 bps.

it obtained through the uart_class structure. This allows us
to declare the uart_class structure as weak and as such allows
us to reference it even when it's not compiled-in.
It also allows is to get the uart_ops structure by name, which
makes it possible to implement the dt tag handling in uart_getenv().
The side-effect of all this is that we're using the uart_class
structure more consistently which means that we now also have
access to the size of the bus space block needed by the hardware
when we map the bus space, eliminating any hardcoding.

that the driver clock is identical to the processor or bus clock.
This is the case for the PowerQUICC processor. When the clock is
high enough, overflows happen in the calculation of the time it
takes to send 1/10 of a character, used in delay loops. Fix the
overflows so as to fix bugs in the delay loops that can cause either
insufficient delays or excessive delays.

  that can be used to check whether receive data is ready, i.e. whether
  the subsequent call of uart_poll() should return a char, and unlike
  uart_poll() doesn't actually receive data.
- Remove the device-specific implementations of uart_poll() and implement
  uart_poll() in terms of uart_getc() and the newly added uart_rxready()
  in order to minimize code duplication.
- In sunkbd(4) take advantage of uart_rxready() and use it to implement
  the polled mode part of sunkbd_check() so we don't need to buffer a
  potentially read char in the softc.
- Fix some mis-indentation in sunkbd_read_char().

Discussed with:	marcel

Missed by:	benno

- Rename REG_DL to REG_DLL and REG_DLH.
- Always treat DLL and DLH as two separate 8-bit registers instead of one
  16-bit register.

Additionally, remove the probe for the high 4 bits of IER being 0 and don't
assume we can always read/write 0 to/from those bits.

These changes allow uart(4) to drive the UARTs on the Intel XScale PXA255.

Reviewed by:	marcel

detection of the FIFO size. Especially for large FIFOs.

	prevents that there's a control flow that leaves the DLAB
	bit set.

the NS8250 class driver. The UART has FIFOs if sc_rxfifosz>1, so
test for that instead.
While here properly initialize sc_rxfifosz and sc_txfifosz in the
case the UART doesn't have FIFOs.

for a character to be received. Instead let getc() do any necesary
locking.

Stop using our local UART_IPEND_* and instead use the global SER_INT_*
as defined in <sys/serial.h>.

<dev/uart_dev_ns8250.h>. The latter can be removed now.

the calculated baudrate. Neither should be 0.

for the console, we emit the actual baudrate during bus enumeration.

with it that need to be understood better before they can be resolved.
This takes time and time is already in short supply.

Reported & tested by: glebius@

size larger than 128 is considered an incompatible size. Stop counting
when we reach 130 in the loop.

does not reliably prevent the triggering of interrupts for all supported
configurations. Thus, the FIFO size probe could cause an interrupt,
which could lead to an interrupt storm in the shared interrupt case.

To prevent this, change ns8250_bus_probe() to use the overflow bit in
the line status register instead of the RX ready bit in the interrupt
identification register to detect whether the FIFO has filled up.
This allows us to clear all bits in the interrupt enable register during
the probe, which should prevent interrupts reliably.
Additionally, the detected FIFO size may be a bit more accurate, because
the overflow bit is only set when the FIFO did actually fill up, while
interrupts would trigger a bit early.

Reviewed and tested on a lot of hardware by:	marcel

checking for transmitter empty.