1. 19 Jan, 2014 1 commit
    • Warner Losh's avatar
      Introduce grab and ungrab upcalls. When the kernel desires to grab the · d76a1ef4
      Warner Losh authored
      console, it calls the grab functions. These functions should turn off
      the RX interrupts, and any others that interfere. This makes mountroot
      prompt work again. If there's more generalized need other than
      prompting, many of these routines should be expanded to do those new
      things.
      
      Should have been part of r260889, but waasn't due to command line typo.
      
      Reviewed by:	bde (with reservations)
      d76a1ef4
  2. 26 Oct, 2013 1 commit
    • Zbigniew Bodek's avatar
      Wait for DesignWare UART transfers completion before accessing line control · 49e368ac
      Zbigniew Bodek authored
      When using DW UART with BUSY detection it is necessary to wait
      until all serial transfers are finished before manipulating the
      line control. LCR will not be affected when UART is busy.
      In addition, if Divisor Latch Access Bit is being set in order to
      modify UART divisors:
      1. We will get BUSY interrupt if interrupts are enabled.
      2. Because LCR will not be affected the THR and (even worse) IER
         contents will be corrupted. This will lead to console hang.
      
      Approved by:	cognet (mentor)
      49e368ac
  3. 30 Aug, 2013 1 commit
    • Marcel Moolenaar's avatar
      A final test with unmodified code has shown that a delay of 150ms · 40a827b6
      Marcel Moolenaar authored
      is not giving us a 100% success rate. Bump the delay to 200ms as
      that seems to do the trick.
      
      Note that during testing the delay was added to uart_bus_attach()
      in uart_core.c. While having the delay in a different place can
      change the behaviour, it was not expected. Having to bump the
      delay with another 50ms could therefore be an indication that
      the problem can not be solved with delays.
      
      Reported by: kevlo@
      Tested by: kevlo@
      40a827b6
  4. 29 Aug, 2013 1 commit
    • Marcel Moolenaar's avatar
      Work-around a timing problem with the ITE IT8513E now that the core · 4fc49975
      Marcel Moolenaar authored
      calls ns8250_bus_ipend() almost immediately after ns8250_bus_attach().
      As it appears, a line break condition is being signalled for almost
      all received characters due to this. A delay of 150ms seems enough
      to allow the H/W to settle and to avoid the problem.
      More analysis is needed, but for now a regression has been addressed.
      
      Reported by: kevlo@
      Tested by: kevlo@
      4fc49975
  5. 21 Aug, 2013 1 commit
  6. 01 Mar, 2013 1 commit
    • Ganbold Tsagaankhuu's avatar
      Add support for A10 uart. · ac4adddf
      Ganbold Tsagaankhuu authored
      A10 uart is derived from Synopsys DesignWare uart and requires
      to read Uart Status Register when IIR_BUSY has detected.
      Also this change includes FDT check, where it checks device
      specific properties defined in dts and sets the busy_detect variable.
      broken_txfifo is also needed to be set in order to make it work for
      A10 uart case.
      
      Reviewed by: marcel@
      Approved by: gonzo@
      ac4adddf
  7. 27 Jan, 2013 1 commit
    • Colin Percival's avatar
      Add a loader tunable "hw.broken_txfifo" which enables a workaround for a · 1c60b24b
      Colin Percival authored
      bug in old versions of QEMU (and Xen, and other places using QEMU code).
      On those buggy emulated UARTs, the "TX idle" interrupt gets lost; with
      this workaround, we spinwait for the TX to happen and then send ourselves
      the interrupt.  It's ugly but it works, while minimizing the impact on
      the code for the !broken_txfifo case.
      
      MFC after:	2 weeks
      1c60b24b
  8. 02 Nov, 2011 1 commit
  9. 26 May, 2011 1 commit
  10. 21 Feb, 2011 1 commit
  11. 19 Oct, 2010 1 commit
  12. 10 May, 2010 1 commit
  13. 02 May, 2010 1 commit
  14. 30 Oct, 2009 1 commit
  15. 08 Apr, 2009 1 commit
  16. 19 Oct, 2008 1 commit
  17. 30 May, 2008 1 commit
    • Benno Rice's avatar
      The XScale PXA255 has three generally ns16x50 compatible UARTs. One of the · 0aefb0a6
      Benno Rice authored
      variations from normal 16x50 behaviour however is the the use of a normally
      unused bit of IER to control RX timeout interrupts independently of the
      generally used RXRDY bit.  If this bit is not enabled, we only ever get
      interrupts when the FIFO is full, never before.  This is not very useful when
      the UART is being used as a console.
      
      In order to support this without causing potential problems on more "normal"
      16x50 variants, this change introduces two hints for the uart device, ier_mask
      and ier_rxbits.  These can be used to override which bits get set and cleared
      when we're enabling and disabling RX interrupts.
      
      Reviewed by:	marcel
      0aefb0a6
  18. 12 Mar, 2008 1 commit
  19. 03 Apr, 2007 1 commit
    • Marcel Moolenaar's avatar
      Don't use a time-limiting loop that's defined in terms of the baudrate · 35777a2a
      Marcel Moolenaar authored
      in the putc() method.  Likewise, in the getc() method, don't check for
      received characters with an interval defined in terms of the baudrate.
      In both cases it works equally well to implement a fixed delay.  More
      importantly, it avoids calculating a delay that's roughly 1/10th the
      time it takes to send/receive a character. The calculation is costly
      and happens for every character sent or received, affecting low-level
      console or debug port performance significantly. Secondly, when the
      RCLK is not available or unreliable, the delays could disrupt normal
      operation.
      
      The fixed delay is 1/10th the time it takes to send a character at
      230400 bps.
      35777a2a
  20. 02 Apr, 2007 1 commit
    • Marcel Moolenaar's avatar
      Don't expose the uart_ops structure directly, but instead have · f8100ce2
      Marcel Moolenaar authored
      it obtained through the uart_class structure. This allows us
      to declare the uart_class structure as weak and as such allows
      us to reference it even when it's not compiled-in.
      It also allows is to get the uart_ops structure by name, which
      makes it possible to implement the dt tag handling in uart_getenv().
      The side-effect of all this is that we're using the uart_class
      structure more consistently which means that we now also have
      access to the size of the bus space block needed by the hardware
      when we map the bus space, eliminating any hardcoding.
      f8100ce2
  21. 28 Mar, 2007 1 commit
    • Marcel Moolenaar's avatar
      For embedded UARTs compatible with the ns8250 family it is possible · ebecffe9
      Marcel Moolenaar authored
      that the driver clock is identical to the processor or bus clock.
      This is the case for the PowerQUICC processor. When the clock is
      high enough, overflows happen in the calculation of the time it
      takes to send 1/10 of a character, used in delay loops. Fix the
      overflows so as to fix bugs in the delay loops that can cause either
      insufficient delays or excessive delays.
      ebecffe9
  22. 18 Jan, 2007 1 commit
    • Marius Strobl's avatar
      - Add a uart_rxready() and corresponding device-specific implementations · 97202af2
      Marius Strobl authored
        that can be used to check whether receive data is ready, i.e. whether
        the subsequent call of uart_poll() should return a char, and unlike
        uart_poll() doesn't actually receive data.
      - Remove the device-specific implementations of uart_poll() and implement
        uart_poll() in terms of uart_getc() and the newly added uart_rxready()
        in order to minimize code duplication.
      - In sunkbd(4) take advantage of uart_rxready() and use it to implement
        the polled mode part of sunkbd_check() so we don't need to buffer a
        potentially read char in the softc.
      - Fix some mis-indentation in sunkbd_read_char().
      
      Discussed with:	marcel
      97202af2
  23. 23 May, 2006 2 commits
  24. 27 Apr, 2006 1 commit
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  28. 30 Mar, 2006 1 commit
  29. 24 Feb, 2006 2 commits
  30. 06 Jan, 2005 1 commit
  31. 20 Nov, 2004 1 commit
  32. 15 Nov, 2004 1 commit
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  35. 26 Jul, 2004 1 commit
  36. 24 Jun, 2004 1 commit
  37. 26 May, 2004 1 commit
    • Thomas Moestl's avatar
      It seems that clearing the MCR_IE bit in the modem control register · 89eef2de
      Thomas Moestl authored
      does not reliably prevent the triggering of interrupts for all supported
      configurations. Thus, the FIFO size probe could cause an interrupt,
      which could lead to an interrupt storm in the shared interrupt case.
      
      To prevent this, change ns8250_bus_probe() to use the overflow bit in
      the line status register instead of the RX ready bit in the interrupt
      identification register to detect whether the FIFO has filled up.
      This allows us to clear all bits in the interrupt enable register during
      the probe, which should prevent interrupts reliably.
      Additionally, the detected FIFO size may be a bit more accurate, because
      the overflow bit is only set when the FIFO did actually fill up, while
      interrupts would trigger a bit early.
      
      Reviewed and tested on a lot of hardware by:	marcel
      89eef2de
  38. 02 Apr, 2004 1 commit