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tobik authored
Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. WWW: https://github.com/cseed/arachne-pnr PR: 227590 Submitted by: Johnny Sorocil <jsorocil@gmail.com> Differential Revision: https://reviews.freebsd.org/D15632
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