Commit be17fcd3 authored by brooks's avatar brooks
Browse files

Upgrade to 4.0.1rc1.

Fix build on powerpc.[0]

Submitted by:	rezny[0]
Differential Revision:	https://reviews.freebsd.org/D10630
parent 28c36ecc
# $FreeBSD$
PORTNAME= llvm
DISTVERSION= 4.0.0
DISTVERSION= 4.0.1rc1
PORTREVISION= 4
CATEGORIES= devel lang
MASTER_SITES= http://llvm.org/${PRE_}releases/${LLVM_RELEASE}/${RCDIR}
......@@ -90,6 +90,7 @@ LLD_DISTFILES= lld-${DISTVERSION}.src${EXTRACT_SUFX}
LLDB_BUILD_DEPENDS= swig:devel/swig13
LLDB_DESC= Install lldb, the LLVM debugger
LLDB_DISTFILES= lldb-${DISTVERSION}.src${EXTRACT_SUFX}
LLDB_EXTRA_PATCHES= ${PATCHDIR}/lldb-patch-tools_lldb_source_Host_common_FileSpec.cpp
LLDB_IMPLIES= CLANG
LLDB_USES= execinfo
LLDB_VARS= _USES_PYTHON=python
......
TIMESTAMP = 1490044553
SHA256 (llvm-4.0.0.src.tar.xz) = 8d10511df96e73b8ff9e7abbfb4d4d432edbdbe965f1f4f07afaf370b8a533be
SIZE (llvm-4.0.0.src.tar.xz) = 21016340
SHA256 (cfe-4.0.0.src.tar.xz) = cea5f88ebddb30e296ca89130c83b9d46c2d833685e2912303c828054c4dc98a
SIZE (cfe-4.0.0.src.tar.xz) = 10900916
SHA256 (compiler-rt-4.0.0.src.tar.xz) = d3f25b23bef24c305137e6b44f7e81c51bbec764c119e01512a9bd2330be3115
SIZE (compiler-rt-4.0.0.src.tar.xz) = 1435104
SHA256 (clang-tools-extra-4.0.0.src.tar.xz) = 41b7d37eb128fd362ab3431be5244cf50325bb3bb153895735c5bacede647c99
SIZE (clang-tools-extra-4.0.0.src.tar.xz) = 583088
SHA256 (lld-4.0.0.src.tar.xz) = 33e06457b9ce0563c89b11ccc7ccabf9cff71b83571985a5bf8684c9150e7502
SIZE (lld-4.0.0.src.tar.xz) = 592728
SHA256 (lldb-4.0.0.src.tar.xz) = 2dbd8f05c662c1c9f11270fc9d0c63b419ddc988095e0ad107ed911cf882033d
SIZE (lldb-4.0.0.src.tar.xz) = 19122324
SHA256 (openmp-4.0.0.src.tar.xz) = db55d85a7bb289804dc42fc5c8e35ca24dfc3885782261b675a194fd7e206e26
SIZE (openmp-4.0.0.src.tar.xz) = 2040104
TIMESTAMP = 1494028453
SHA256 (llvm-4.0.1rc1.src.tar.xz) = e07bde6275d862642ec640d146358c2bd4cc99513d74f7b897364c5ff14bb5ec
SIZE (llvm-4.0.1rc1.src.tar.xz) = 21065084
SHA256 (cfe-4.0.1rc1.src.tar.xz) = 82148c2ccd7e59eb631dd2f1941097ef96154f251b7aa09a3191ebd7788e3f94
SIZE (cfe-4.0.1rc1.src.tar.xz) = 10933060
SHA256 (compiler-rt-4.0.1rc1.src.tar.xz) = bf7dc6abe0be57a3d2600033c873021058a11cb96517984e0f7c6cd1ea06a2d7
SIZE (compiler-rt-4.0.1rc1.src.tar.xz) = 1428764
SHA256 (clang-tools-extra-4.0.1rc1.src.tar.xz) = a80f4f24f779755bdd25b4fd62a50391a303823a09cc629061e73e795f1c92c1
SIZE (clang-tools-extra-4.0.1rc1.src.tar.xz) = 581696
SHA256 (lld-4.0.1rc1.src.tar.xz) = 5439ee1556a7572a28d0bfe7a391dd9918c6d75f4501bb5e04c4bc50314b2e25
SIZE (lld-4.0.1rc1.src.tar.xz) = 593192
SHA256 (lldb-4.0.1rc1.src.tar.xz) = e4b328173bd6493be8669648dc82f337a560c63ac7ade66ee2fdcabaac03553f
SIZE (lldb-4.0.1rc1.src.tar.xz) = 19089272
SHA256 (openmp-4.0.1rc1.src.tar.xz) = 0bda10d7fca817ba19d2fc63170621567b10da7bf52988f7d3cef09a5e50bfb0
SIZE (openmp-4.0.1rc1.src.tar.xz) = 2275312
--- tools/lldb/source/Host/common/FileSpec.cpp.orig 2017-04-03 04:25:09 UTC
+++ tools/lldb/source/Host/common/FileSpec.cpp
@@ -17,6 +17,7 @@
#include <libgen.h>
#endif
#include <fstream>
+#include <limits.h>
#include <set>
#include <string.h>
------------------------------------------------------------------------
r300404 | dim | 2017-04-15 22:15:01 +0000 (Sat, 15 Apr 2017) | 22 lines
Use correct registers for "A" inline asm constraint
Summary:
In PR32594, inline assembly using the 'A' constraint on x86_64 causes
llvm to crash with a "Cannot select" stack trace. This is because
`X86TargetLowering::getRegForInlineAsmConstraint` hardcodes that 'A'
means the EAX and EDX registers.
However, on x86_64 it means the RAX and RDX registers, and on 16-bit x86
(ia16?) it means the old AX and DX registers.
Add new register classes in `X86RegisterInfo.td` to support these cases,
and amend the logic in `getRegForInlineAsmConstraint` to cope with
different subtargets. Also add a test case, derived from PR32594.
Reviewers: craig.topper, qcolombet, RKSimon, ab
Reviewed By: ab
Subscribers: ab, emaste, royger, llvm-commits
Differential Revision: https://reviews.llvm.org/D31902
------------------------------------------------------------------------
Index: test/CodeGen/X86/inline-asm-A-constraint.ll
===================================================================
--- test/CodeGen/X86/inline-asm-A-constraint.ll (nonexistent)
+++ test/CodeGen/X86/inline-asm-A-constraint.ll (revision 300404)
@@ -0,0 +1,35 @@
+; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64--"
+
+; Function Attrs: nounwind uwtable
+define { i64, i64 } @foo(i8* %ptr, i128* nocapture readonly %src, i128* nocapture readonly %dst) local_unnamed_addr #0 {
+entry:
+ %0 = load i128, i128* %dst, align 16, !tbaa !1
+ %shr = lshr i128 %0, 64
+ %conv = trunc i128 %shr to i64
+ %conv1 = trunc i128 %0 to i64
+ %1 = load i128, i128* %src, align 16, !tbaa !1
+ %2 = tail call i128 asm sideeffect "lock; cmpxchg16b $1", "=A,=*m,{cx},{bx},0,*m,~{dirflag},~{fpsr},~{flags}"(i8* %ptr, i64 %conv, i64 %conv1, i128 %1, i8* %ptr) #1, !srcloc !5
+ %retval.sroa.0.0.extract.trunc = trunc i128 %2 to i64
+ %retval.sroa.2.0.extract.shift = lshr i128 %2, 64
+ %retval.sroa.2.0.extract.trunc = trunc i128 %retval.sroa.2.0.extract.shift to i64
+ %.fca.0.insert = insertvalue { i64, i64 } undef, i64 %retval.sroa.0.0.extract.trunc, 0
+ %.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %retval.sroa.2.0.extract.trunc, 1
+ ret { i64, i64 } %.fca.1.insert
+}
+; CHECK: lock
+; CHECK-NEXT: cmpxchg16b
+
+attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 5.0.0 (trunk 300088)"}
+!1 = !{!2, !2, i64 0}
+!2 = !{!"__int128", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C/C++ TBAA"}
+!5 = !{i32 269}
Index: lib/Target/X86/X86RegisterInfo.td
===================================================================
--- lib/Target/X86/X86RegisterInfo.td (revision 300403)
+++ lib/Target/X86/X86RegisterInfo.td (revision 300404)
@@ -437,8 +437,10 @@
def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
(add LOW32_ADDR_ACCESS, RBP)>;
-// A class to support the 'A' assembler constraint: EAX then EDX.
+// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
+def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
+def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
// Scalar SSE2 floating point registers.
def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp (revision 300403)
+++ lib/Target/X86/X86ISelLowering.cpp (revision 300404)
@@ -35917,10 +35917,20 @@
return Res;
}
- // 'A' means EAX + EDX.
+ // 'A' means [ER]AX + [ER]DX.
if (Constraint == "A") {
- Res.first = X86::EAX;
- Res.second = &X86::GR32_ADRegClass;
+ if (Subtarget.is64Bit()) {
+ Res.first = X86::RAX;
+ Res.second = &X86::GR64_ADRegClass;
+ } else if (Subtarget.is32Bit()) {
+ Res.first = X86::EAX;
+ Res.second = &X86::GR32_ADRegClass;
+ } else if (Subtarget.is16Bit()) {
+ Res.first = X86::AX;
+ Res.second = &X86::GR16_ADRegClass;
+ } else {
+ llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
+ }
return Res;
}
return Res;
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