This project is mirrored from https://gitlab.com/x86-psABIs/x86-64-ABI.git. Pull mirroring updated .
  1. 20 Dec, 2021 1 commit
  2. 18 Oct, 2021 2 commits
  3. 13 Oct, 2021 1 commit
    • Michael Matz's avatar
      syscalls don't clobber argument regs · bdce759a
      Michael Matz authored
      Since 2001 the kernel was saving/restoring most registers and glibc
      made use of this, i.e. it expects only rcx and r11 to be clobbered.
      Let's clarify the wording to that effect.
      bdce759a
  4. 19 Jul, 2021 1 commit
  5. 24 May, 2021 1 commit
  6. 03 May, 2021 1 commit
  7. 09 Mar, 2021 2 commits
  8. 05 Mar, 2021 1 commit
    • Michael Matz's avatar
      Use "return address" · 82df0ba5
      Michael Matz authored
      to describe what's pushed by the call instruction, the return value is
      conventionally the value sitting in %rax after return.
      82df0ba5
  9. 22 Feb, 2021 1 commit
    • Lukas Diekmann's avatar
      Clarify stack frame alignment for function calls. · 450fbe9f
      Lukas Diekmann authored
      Previously, the moment at which the stack needs to be aligned to 16 (32
      or 64) bytes could be interpreted as both before and after the call
      instruction is executed. This commit attempts to make this clearer, by
      stating explicitly that the alignment is required immediately before the
      call instruction.
      450fbe9f
  10. 31 Aug, 2020 3 commits
    • H.J. Lu's avatar
      Remove a duplicated line · 1ad6252f
      H.J. Lu authored
      There are:
      
      \item The 64-bit mantissa of arguments of type \code{long double}
      \item The 64-bit mantissa of arguments of type \code{long double}
      1ad6252f
    • H.J. Lu's avatar
      Document the %fs segment register as the thread pointer · c506311c
      H.J. Lu authored
      The %fs segment register is used to implement the thread pointer.  The
      linear address of the thread pointer is stored at offset 0 relative to
      the %fs segment register.
      c506311c
    • H.J. Lu's avatar
      Document Intel AMX · 72a164b9
      H.J. Lu authored
      Intel Advanced Matrix Extensions (Intel AMX) is a new programming
      paradigm consisting of two components: a set of 2-dimensional registers
      (tiles) representing sub-arrays from a larger 2-dimensional memory image,
      and accelerators able to operate on tiles.  Capability of Intel AMX
      implementation is enumerated by palettes.  Two palettes are supported:
      palette 0 represents the initialized state and palette 1 consists of
      8 tile registers of up to 1 KB size, which is controlled by a tile
      control register.
      72a164b9
  11. 03 Aug, 2020 3 commits
  12. 24 Jul, 2020 1 commit
  13. 04 May, 2020 1 commit
  14. 19 Jan, 2020 1 commit
  15. 11 Jul, 2019 1 commit
  16. 11 Apr, 2019 1 commit
    • H.J. Lu's avatar
      Document the maximum aligned boundary · 300bfb41
      H.J. Lu authored
      The maximum aligned boundary is the maximum alignment of all variable
      passed on stack and arguments passed on stack should be properly aligned.
      300bfb41
  17. 01 Mar, 2019 2 commits
  18. 12 Jun, 2018 1 commit
    • susematz's avatar
      Create README.md · f70ec56d
      susematz authored
      add some info for contacting us and building the pdf.
      f70ec56d
  19. 08 Feb, 2018 3 commits
  20. 29 Jan, 2018 12 commits