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Zero-width bit-fields are NO_CLASS, instead of INTEGER, for class merging
purposes.

Since 2001 the kernel was saving/restoring most registers and glibc
made use of this, i.e. it expects only rcx and r11 to be clobbered.
Let's clarify the wording to that effect.

GCC has

 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)

and

   (AX_REG                       0)
   (DX_REG                       1)

Add a footnote to describe that GCC uses RAX and RDX to pass arguments
to the landing pad.

This fixes:

https://gitlab.com/x86-psABIs/x86-64-ABI/-/issues/9

Complex __float128 is passed as if:

struct complex __float128 {
  __float128 real;
  __float128 imag;
};

Interestingly, efe89e3c fixed a typo just one word apart
but didn't notice this one.

Now to see what that looks like ...

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>

to describe what's pushed by the call instruction, the return value is
conventionally the value sitting in %rax after return.

Previously, the moment at which the stack needs to be aligned to 16 (32
or 64) bytes could be interpreted as both before and after the call
instruction is executed. This commit attempts to make this clearer, by
stating explicitly that the alignment is required immediately before the
call instruction.

There are:

\item The 64-bit mantissa of arguments of type \code{long double}
\item The 64-bit mantissa of arguments of type \code{long double}

The %fs segment register is used to implement the thread pointer.  The
linear address of the thread pointer is stored at offset 0 relative to
the %fs segment register.

Intel Advanced Matrix Extensions (Intel AMX) is a new programming
paradigm consisting of two components: a set of 2-dimensional registers
(tiles) representing sub-arrays from a larger 2-dimensional memory image,
and accelerators able to operate on tiles.  Capability of Intel AMX
implementation is enumerated by palettes.  Two palettes are supported:
palette 0 represents the initialized state and palette 1 consists of
8 tile registers of up to 1 KB size, which is controlled by a tile
control register.

The concept was described in this mailing list thread:

https://sourceware.org/pipermail/libc-alpha/2020-July/116135.html

The names of the CPU features come from this document:

Intel® 64 and IA-32 Architectures Software Developer’s Manual
Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4
Submitted: May 01, 2018, Last updated: May 27, 2020
https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4.html

This switches to CPUID bit names where available.  Formatting
is adjusted to match the other tables.

TSC is dropped because its reliability changed since the initial
release of the architecture due to virtualization.

Kernel mode features are removed due to their complex interaction
with virtualization.

Changes to this document made by Intel Corporation are copyright Intel
Corporation and licensed under CC BY 4.0:

https://creativecommons.org/licenses/by/4.0/legalcode

Pass and return _Float16 values in XMM registers.

LEA instruction with R_X86_64_GOTPC32_TLSDESC relocation must be encoded
with REX prefix even if it isn't required by destination register.  If
the LEA encoding has a variable length, linker can't tell where it starts
and can't safely perform GDesc -> IE/LE optimization.  See;

https://sourceware.org/bugzilla/show_bug.cgi?id=25416

The maximum aligned boundary is the maximum alignment of all variable
passed on stack and arguments passed on stack should be properly aligned.

The Linux kernel may align the end of the input argument area to a
8, instead of 16, byte boundary.

add some info for contacting us and building the pdf.

R_I386_GOTPC is a typo.  It should be R_386_GOTPC.

	* object-files.tex (Relocation Types): Rename R_I386_GOTPC to
	R_386_GOTPC.

	* object-files.tex: Refer STT_GNU_IFUNC to Linux Extensions to
	gABI.

Don't use ChangeLog files.  Instead, put the ChangeLog entries in
git commit message.

The TT font actually feels a bit larger then the normal serif font,
so it can be reduced in size a bit without hampering visual flow.
Also change some examples to remove superfluous spacing, and from
tables redundant entries.  Use the geometry package, which in itself
reduces the large margins a bit already.  Don't explicitely reduce
margins further, as the current setting gives a sensible line-length
for one-column layout.

For small and medium models, different code sequences used to avoid PLT
for calling external functions so that GOT can be read-only after symbol
resolution.  TLS code sequences for general and local dynamic models are
updated to replace direct call to __tls_get_addr via the PLT entry with
indirect call to __tls_get_addr via the GOT slot.

	* Makefile (INCLUDES): Add x32.tex and secure.tex.
	* abi.tex: Include secure.
	* dl.tex (Global Offset Table): Add a label.
	(Procedure Linkage Table): Likewise.
	* secure.tex: New file.

indirectly when they have non-trivial or deleted move constructors, or
deleted copy constructors or destructors.

Fixes #6.

	* Makefile (INCLUDES): Add x32.tex mpx.tex.

the Makerules should always run in nonstopmode.  Also add
-file-line-error.  In case anyones TeX defaults are different.

* libraries.tex (Unwind Library Interface): Add
_Unwind_GetIPInfo.

Convert mov to mov for symbol defined locally in the lower
32-bit address space when PIC is off.

This restores r251 from the master svn repo of the x86-64 psABI,
whose server is gone.  r251 was the last committed version in that
repo before the server went away (at the point of this commit,
2018-01-29).

(and add abi.cb2)